English

RISC Microprocessors

This book discusses the Reduced Instruction Set Computer architecture, a technique to streamline instruction execution. Sometimes, RISC is said to stand for “Relegate Important Stuff to the Compiler,” since the compilation process is done offline, and then the code is run. The time penalty paid at compile time is paid back by faster code execution. RISC machines place more burdens on their compilers. The alternative to RISC is CISC – Complex Instruction Set Computer. An example of CISC would be the legacy Intel x86, IA-32 instruction set. Even that is now translated on the fly to internal RISC format. This book assumes a general familiarity with computer architecture and instruction execution. A glossary of terms, and selected references are provided.

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